As the width of metal lines are further scaled down to submicron and nanometer dimensions, electromigration failure and joule heating may lead to integrated circuit failure. Thus, copper which has lower bulk resistivity, higher melting point, and higher heat conductivity than aluminum is considered more viable for fine line metallization.
Referring to FIGS. 1A and 1B, FIG. 1A shows a top view of a copper line 10, and FIG. 1B shows a cross sectional view of the copper line 10 of FIG. 1A along line AA. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper line 10 is typically formed by etching a trench 12 as an opening within a trench insulating layer 14. The trench 12 is then filled with copper to form the metal line 10.
The trench insulating layer 14 is typically a silicon dioxide layer that is formed on a silicon substrate 16. However, the present invention may be practiced when copper is also formed in any other type of trench insulating layer that is formed on any other type of semiconductor material, as would be apparent to one of ordinary skill in the art from the description herein.
Referring to FIG. 1C, the copper line 10 is part of a larger integrated circuit that is fabricated within a semiconductor wafer 18. After the trench 12 is filled with copper, the surface of the semiconductor wafer 16 is polished with a chemical mechanical polish to confine the copper to be contained within the trench 12, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 1A, after the chemical mechanical polish of the semiconductor wafer 16, copper residue 20 remains on the surfaces of the semiconductor wafer 16. The copper residue 20 includes any one of dicopper oxide (Cu.sub.2 O), copper oxide (CuO), and an organic copper complex such as copper benzotriazole (Cu-BTA) that results from copper deposition and polishing processes having organic solvents.
Some of the copper residue 20 remains on the back-side of the semiconductor wafer 18. Some of the copper residue 20 becomes ingrained into the top surface of the silicon dioxide trench insulating layer 14 after the chemical mechanical polish of the semiconductor wafer 18. Some of the copper residue 20 remains on top of the copper line 10.
In any case, such copper residue may adversely affect the circuit performance of the integrated circuit within the semiconductor wafer 18. For example, the copper residue 20 ingrained into the silicon dioxide trench insulating layer 14 degrades the insulating property of the silicon dioxide trench insulating layer 14. The copper residue 20 on the backside of the semiconductor wafer 16 may alter the properties of the semiconductor substrate 16 by introducing impurities into the semiconductor substrate 16. The copper residue 20 on top of the copper line 10 may prevent a good metal contact of a via plug to the top of copper line 10 having the copper residue 20.
In the prior art, a process for removing the copper residue 20 included rinsing the semiconductor wafer 18 in deionized water after a chemical mechanical polish. However, such a rinsing process does not adequately remove the copper residue 20 from surfaces of the semiconductor wafer 18.